Ethernet switches are multi-port devices that are utilized in networks. The switches provide connections to several clients simultaneously. Each of the switches typically include Media Access Controller (MAC) devices that interface with Physical (PHY) devices. Typically, these devices require a specified number of pins to interface one MAC device with one PHY device. In addition, as the overall speed of the network increases generally the number of pins required for the interfaces also increases. Both of these factors generally increase the cost of the resultant switch. To illustrate these problems with an example, refer now to FIG. 1 in conjunction with the following discussion.
FIG. 1 is a block diagram of a six (6) port Ethernet switch 10. The switch 10 comprises a switch fabric 12, six IEEE 802.3 Media Access Control (MAC) devices 14 and six individual Physical (PHY) devices 16. Each PHY device as is seen is connected to a station 18. Each MAC device 14 connects to a corresponding PHY device 16 using several electrical connections. Typically, 10 Mbps MAC/PHY connections require 7 pins and 100 Mbps MAC/PHY connections require 18 pins.
Current generations of switch devices generally provide separate silicon pieces for the MAC and the PHY. As silicon processes improve, both the MAC functions and the PHY functions become integrated, often resulting in a single piece of silicon containing multiple (e.g., 4) MACs and multiple PHYs (e.g., 4).
As shown in FIG. 1, when multiple MAC devices 14 need to be connected to multiple PHY devices 16, a separate serial interface 20 is required for every MAC/PHY connection. Therefore, as the total number of device pairs increases or as the integration of PHY devices and MAC devices increases, the total pin count grows linearly. For example, a 10 Mbps quad physical layer device connected to a quad 10 Mbps MAC device will require a total of 28 pins and octal devices will require 56 pins. For 100 Mbps connections, the problem increases dramatically, a quad 100 Mbps MAC/PHY interconnect will require a total of 72 pins and octal devices will require 144 pins. Increasing the pin count generally increases the package size, resulting in an increase in silicon and system cost. Therefore, it is beneficial to provide a method and system to reduce the number of total pins required for highly integrated MAC/PHY devices.
Accordingly, what is needed is a method and system that allows for a reduced pin count for the MAC/PHY connections in conventional networks as well as when network speeds increase. The system and method should be cost effective, easily implemented and compatible with existing network architectures.The present invention addresses such a need.